Need help with Systemverilog

I got these errors. Please help. :)

module test;
	string s;
	byte queue;
endmodule

Error (10911): SystemVerilog Unsupported Feature error at test.sv(7): Integrated Synthesis does not support declaring string variables outside functions and tasks
Error (10170): Verilog HDL syntax error at test.sv(8) near text "$";  expecting an operand