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Altera_Forum
Honored Contributor
Honored ContributorNeed help with Systemverilog
I got these errors. Please help. :)
module test;
string s;
byte queue;
endmodule
Error (10911): SystemVerilog Unsupported Feature error at test.sv(7): Integrated Synthesis does not support declaring string variables outside functions and tasks
Error (10170): Verilog HDL syntax error at test.sv(8) near text "$"; expecting an operand
2 Replies
Altera_ForumRead the error message.
It says "synthesis", so that implies you're getting this error from Quartus. Try your code in Modelsim instead. Cheers, Dave- Altera_Forum
Thank you. :D
