need help of the readmemb function in verilog

Thanks for your kindly help. The code works well.

BTW, I find it also works if I remove the "for" loop, just use readmemb function once.

Thanks a lot for your suggestions.

Regards,

Lyila

Thank you sooo much. The code works know.

Thanks and regard,

Lyila

--- Quote Start ---

Hi,

I wrote a code to read data from a .txt file and output the data to the AD/DA card. But the output of the module is a constant value. (the text file has 8192 binary numbers with different value).

Can I get some help? This is really urgent:confused:.

Truly appreciate your kindly help.

Thanks.

Following is my code.

module readfile ( clock,data_out);

input clock;

output [13:0] data_out;

parameter size = 8192; //data size

reg [13:0] read_mem[1:size];

reg [13:0] data_out;

integer a;

initial

$readmemb ("data.txt", read_mem);

always @(posedge clock)

begin

for (a=1; a<size+1; a=a+1)

begin

if (clock) // output frequency depends on the frequency of the input clock

data_out <= read_mem[a];

end

end

endmodule

Many many thanks./QUOTE]

Hi,

i have written an example for you were you can seee howt could work:

module read_file ( clock,data_out);

input clock;

output [13:0] data_out;

parameter size = 10; //data size 8192

reg [13:0] read_mem;

reg [13:0] data_out;

integer a;

// ROM generation

// ROM is filled with the data of the text file

initial

begin

for (a=0; a<size; a=a+1)

$readmemb ("data.txt", read_mem);

end

// ROM is read continuously

reg [9:0] i;

always@(posedge clock)

begin

data_out<= read_mem[i];

i <= i + 1;

end

endmodule

You always have to keep in mind that your code is converted to hardware. That means

for the intial part Quartus generates a ROM, filled with the data of the text file. That means

every time when you would like to change the data, you have to run Quartus again.

In order to see the data continuously you have to read every clock cycle one address of

your ROM.

BTW: the default loop limit is 5000. If you need more you have to change the setting in Quartus.

One way to do that is:

Assignments -> Settings -> Analyse & Synthesis Settings -> more -> look for "Iteration limit for constant Verilog loops.

Kind regards

GPK

this code will output data repeatedly.

when i==8191, i=i+1 will result in 0 because i is 13-bit width.

Thanks for your help, loywong.

I'll test the code to see if I can get the correct output.

If I need to output the data repeatedly, how can I change the code?

Thanks again.

there is no problems with your memory initializing if you have a correct format of "data.txt".

but you misunderstood the function of keyword "for", it describes implementing repeation of hardware but not cycle of procedure as in "c" language.

I guess you got a constant of the last word in your memory, right?

you should wrote:

reg [12 : 0] i;

always@(posedge clk)

begin

data_out <= read_mem[i + 1];

i <= i + 1;

end