need help of the readmemb function in verilog

there is no problems with your memory initializing if you have a correct format of "data.txt".

but you misunderstood the function of keyword "for", it describes implementing repeation of hardware but not cycle of procedure as in "c" language.

I guess you got a constant of the last word in your memory, right?

you should wrote:

reg [12 : 0] i;

always@(posedge clk)

begin

data_out <= read_mem[i + 1];

i <= i + 1;

end