--- Quote Start ---
Hi,
I wrote a code to read data from a .txt file and output the data to the AD/DA card. But the output of the module is a constant value. (the text file has 8192 binary numbers with different value).
Can I get some help? This is really urgent:confused:.
Truly appreciate your kindly help.
Thanks.
Following is my code.
module readfile ( clock,data_out);
input clock;
output [13:0] data_out;
parameter size = 8192; //data size
reg [13:0] read_mem[1:size];
reg [13:0] data_out;
integer a;
initial
$readmemb ("data.txt", read_mem);
always @(posedge clock)
begin
for (a=1; a<size+1; a=a+1)
begin
if (clock) // output frequency depends on the frequency of the input clock
data_out <= read_mem[a];
end
end
endmodule
Many many thanks./QUOTE]
Hi,
i have written an example for you were you can seee howt could work:
module read_file ( clock,data_out);
input clock;
output [13:0] data_out;
parameter size = 10; //data size 8192
reg [13:0] read_mem;
reg [13:0] data_out;
integer a;
// ROM generation
// ROM is filled with the data of the text file
initial
begin
for (a=0; a<size; a=a+1)
$readmemb ("data.txt", read_mem);
end
// ROM is read continuously
reg [9:0] i;
always@(posedge clock)
begin
data_out<= read_mem[i];
i <= i + 1;
end
endmodule
You always have to keep in mind that your code is converted to hardware. That means
for the intial part Quartus generates a ROM, filled with the data of the text file. That means
every time when you would like to change the data, you have to run Quartus again.
In order to see the data continuously you have to read every clock cycle one address of
your ROM.
BTW: the default loop limit is 5000. If you need more you have to change the setting in Quartus.
One way to do that is:
Assignments -> Settings -> Analyse & Synthesis Settings -> more -> look for "Iteration limit for constant Verilog loops.
Kind regards
GPK
Honored Contributor
