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Altera_Forum's avatar
Altera_Forum
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17 years ago

need help for my project

below is given restoring method code and its algo(its link)

there is no error in the programme but output is not comming right

please any one can give me hint why it is not coming right

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity dev1 is

port(a,b: in std_logic_vector(3 downto 0):="0000";

quo : inout std_logic_vector(3 downto 0):="0000";

rem1: inout std_logic_vector(4 downto 0):="00000");

end dev1;

architecture dev1 of dev1 is

begin

process(a,b)

variable false:boolean;

begin

rem1<="00000";

quo <= a;

if(a="0000" and b="0000") then

assert false

report"intermedite result"

severity error;

quo <= "XXXX";

rem1 <= "XXXXX";

elsif( b="0000") then

assert false

report "infinity"

severity error;

quo<="XXXX";

rem1<="XXXXX";

else

for k in 3 downto 0 loop

rem1<=rem1(3 downto 0) & quo(3); --shifting of rem1 and quo together by 1 means

quo<=quo(2 downto 0) & '0'; -- in lsb of rem1 putting msb of quo and lsb of quoputting 0

rem1 <= rem1 - b;

if(rem1(4) = '0') then --if rem1 is +ive means msb of quo is zero

quo(0)<='1'; -- make lsb of quo one

else

rem1 <= rem1 + b; --if rem is negative means msb of quo is 1

-- restore the remainder

end if;

end loop;

end if;

end process;

end;

ALGORITHM(restoring method)

Step 1: Take dividend & divisor as input.

Step 2: Initialize remainder to zero & quotient to dividend.

Step 3: If b is zero then display invalid divisor.

Step 4: Else shift remainder & quotient to 1 bit left.

Step 5: Then check if remainder is negative then subtract divisor from

remainder.

Else add divisor to remainder.

Step 6: If remainder is negative then make LSB of quotient 0 .

Else make LSB of quotient 1.

Step 7: Repeat steps 4 to 6 n times where n is the number of bits in

dividend.

Step 8: If remainder is negative then restore it i.e add divisor to it.

Step 9: Display remainder and quotient.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    According to VHDL rules, the result of a <= signal assignments in process takes effect on exiting the process. Multiple assignments are allowed, but only the last is valid.

    To have the intermediate results updated for the next iteration, variables have to be used.

    The modfied code below gives correct results, as far as I see.

    The exeption handling has no meaning for the synthesized code and is apparently ignored in Quartus integrated simulator. It should have a meaning in ModelSim simulation. 

    library ieee;
use ieee.std_logic_1164.all;construct 
use ieee.std_logic_unsigned.all;
entity dev1 is
port(a,b: in std_logic_vector(3 downto 0):="0000";
quo : out std_logic_vector(3 downto 0);
rem1: out std_logic_vector(4 downto 0));
end dev1;
architecture dev1 of dev1 is
begin
process(a,b)
variable false:boolean;
variable q : std_logic_vector(3 downto 0);
variable r : std_logic_vector(4 downto 0);
begin
r:="00000";
q:= a;
for k in 3 downto 0 loop
r:=r(3 downto 0) & q(3); --shifting of rem1 and quo together by 1 means
q:=q(2 downto 0) & '0'; -- in lsb of rem1 putting msb of quo and lsb of quoputting 0
r := r - b;
if(r(4) = '0') then --if rem1 is +ive means msb of quo is zero 
q(0):='1'; -- make lsb of quo one
else 
r := r + b; --if rem is negative means msb of quo is 1 
-- restore the remainder 
end if;
end loop;
rem1 <= r;
quo <= q;
end process;
end;

    P.S.: I compared the Quartus V8.1 implementation of your code with lpm_div Megafunction. With MAX II, lpm_div needed 24 LEs while your code requires 41 LEs. Generally, Quartus Megafunction can be expected to produce code with maximum optimization.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi Anupamasia,

    Your code looks like a C-program written in VHDL.

    You will need to forget about C-style completely and think of RTL, registers in hardware...etc.

    Here are some notes:

    1) input a is in effect doing nothing.

    2) there is no clock in your design and so no rgisters yet synchronous design is the backbone of all fpga design today. You are asking for a shift and this requires clocked registers...

    3) with multiple sequential assignments in a process only the last one is taken in by the compiler to update the node. Any assignments before that are ignored at compile time.

    4) the loop in your program will do nothing like shift because it is simply sequential assignment to same nodes.

    The expression:

    rem1<=rem1(3 downto 0) & quo(3);

    is ok by itself in a clocked process without the loop...

    kaz
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    You are asking for a shift and this requires clocked registers...

    --- Quote End ---

    Not actually. In VHDL, a loop can also be a design method for a combinational process.

    You didn't consider the option of creating a pure combinational divider, as in the lpm_div Megafunction. With the modifications shown above, the example is converted into a usable design. A sequential clocked divider is another option, of course.