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Altera_Forum
Honored Contributor
Honored Contributorneed help for my project
below is given restoring method code and its algo(its link) there is no error in the programme but output is not comming right please any one can give me hint why it is not coming right lib...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You are asking for a shift and this requires clocked registers... --- Quote End --- Not actually. In VHDL, a loop can also be a design method for a combinational process. You didn't consider the option of creating a pure combinational divider, as in the lpm_div Megafunction. With the modifications shown above, the example is converted into a usable design. A sequential clocked divider is another option, of course.
