need help for my project

According to VHDL rules, the result of a <= signal assignments in process takes effect on exiting the process. Multiple assignments are allowed, but only the last is valid.

To have the intermediate results updated for the next iteration, variables have to be used.

The modfied code below gives correct results, as far as I see.

The exeption handling has no meaning for the synthesized code and is apparently ignored in Quartus integrated simulator. It should have a meaning in ModelSim simulation.

library ieee;
use ieee.std_logic_1164.all;construct 
use ieee.std_logic_unsigned.all;
entity dev1 is
port(a,b: in std_logic_vector(3 downto 0):="0000";
quo : out std_logic_vector(3 downto 0);
rem1: out std_logic_vector(4 downto 0));
end dev1;
architecture dev1 of dev1 is
begin
process(a,b)
variable false:boolean;
variable q : std_logic_vector(3 downto 0);
variable r : std_logic_vector(4 downto 0);
begin
r:="00000";
q:= a;
for k in 3 downto 0 loop
r:=r(3 downto 0) & q(3); --shifting of rem1 and quo together by 1 means
q:=q(2 downto 0) & '0'; -- in lsb of rem1 putting msb of quo and lsb of quoputting 0
r := r - b;
if(r(4) = '0') then --if rem1 is +ive means msb of quo is zero 
q(0):='1'; -- make lsb of quo one
else 
r := r + b; --if rem is negative means msb of quo is 1 
-- restore the remainder 
end if;
end loop;
rem1 <= r;
quo <= q;
end process;
end;

P.S.: I compared the Quartus V8.1 implementation of your code with lpm_div Megafunction. With MAX II, lpm_div needed 24 LEs while your code requires 41 LEs. Generally, Quartus Megafunction can be expected to produce code with maximum optimization.