need help for my project

Hi Anupamasia,

Your code looks like a C-program written in VHDL.

You will need to forget about C-style completely and think of RTL, registers in hardware...etc.

Here are some notes:

1) input a is in effect doing nothing.

2) there is no clock in your design and so no rgisters yet synchronous design is the backbone of all fpga design today. You are asking for a shift and this requires clocked registers...

3) with multiple sequential assignments in a process only the last one is taken in by the compiler to update the node. Any assignments before that are ignored at compile time.

4) the loop in your program will do nothing like shift because it is simply sequential assignment to same nodes.

The expression:

rem1<=rem1(3 downto 0) & quo(3);

is ok by itself in a clocked process without the loop...

kaz