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Altera_Forum
Honored Contributor
Honored ContributorNCO reset_n
Quartus II v12.0, Cyclone III, NCO v12.0, Small ROM, no modulation, no dithering, no hopping, 16-bit sine and cosine outputs, 24MHz clock:
Nco_ug.pdf says reset_n is an active-low asynchronous reset, and Quartus II seems to think it is asynchronous because I have gotten a warning about it. But I see the outputs reset on the leading edge of the clock when reset_n is low. Is reset_n actually synchronous?4 Replies
Altera_ForumIt could be you are releasing the reset as such or you are pre-synchronising it and that is good. If not then the outputs themselves are not under reset but some other internal nco logic e.g. accummulator.
- Altera_Forum--- Quote Start --- Is reset_n actually synchronous? --- Quote End --- No, the documentation is wrong in this regard. As far as I'm aware of, the NCO reset is mostly synchronous and partly asynchronous. A usual synchronously released reset should cause no problems.
- Altera_Forum
So are (invisible) registers within the NCO reset asynchronously but the outputs change on the next leading edge of the clock?
- Altera_Forum
I am pretty sure there's a reset synchronizer on the reset_n circuit, so You assert reset asynchronously and it's then sync'ed t the input clock.
