Honored ContributorQuartus II v12.0, Cyclone III, NCO v12.0, Small ROM, no modulation, no dithering, no hopping, 16-bit sine and cosine outputs, 24MHz clock:
Nco_ug.pdf says reset_n is an active-low asynchronous reset, and Quartus II seems to think it is asynchronous because I have gotten a warning about it. But I see the outputs reset on the leading edge of the clock when reset_n is low. Is reset_n actually synchronous?
Honored ContributorIt could be you are releasing the reset as such or you are pre-synchronising it and that is good. If not then the outputs themselves are not under reset but some other internal nco logic e.g. accummulator.
Honored ContributorHonored ContributorSo are (invisible) registers within the NCO reset asynchronously but the outputs change on the next leading edge of the clock?
Honored ContributorI am pretty sure there's a reset synchronizer on the reset_n circuit, so You assert reset asynchronously and it's then sync'ed t the input clock.
