My First CPU but.. one problem

There are two possibilities for an 'X' condition in multisim.

1. The signal is uninitialized, therefore the value is unknown and 'X'.

2. The signal is in contention with one side driving a '1' and the other driving a '0'. Multisim can't determine the resulting state and indicates unknown ('X')

You are having issues with contention. When we_synth is set to '1', you must wait one clock for your ram to place the data bus in high impedance before applying data.

It may be a good idea to use a RAM with a data in port and a data out port instead of a single bidirectional data port. This way, you can avoid using 'Z' inside your design (for the RAM interface at least).

Just so you know - the blue areas are times of high impedance. ('Z')

Thank you very much for your valuable informations.

I've adjusted code and removed red warning in Modelsim with:

case state is
	-- ...
	when sexec =>				
		-- Read data
		case data(7 downto 6) is
			-- ...
			-- Store
			when "01" => 
				we 	<= '1';					
				addr 	<= data(5 downto 0);							
				state <= sstore;
			-- ...
		end case;						
	when sstore =>
		-- write to memory, data is ready next clock								
		data 	<= reg;
		state <= sfetch;
	when others => null;
end case;

I just moved:

data <= reg;

In the state sstore.

So using high impedance Z signals in design is a worst practice?

Thank you

High impedance should only be used on external pins when it is required (usually on a bidirectional bus).

On internal signals the FPGA hardware isn't capable of putting a line in high impedance, so if you use it the synthesizer will change it to OR gates. It is absolutely possible to use it inside an FPGA design but it is considered bad practise because it doesn't correspond to the generated hardware.