My First CPU but.. one problem

Thank you very much for your valuable informations.

case state is
	-- ...
	when sexec =>				
		-- Read data
		case data(7 downto 6) is
			-- ...
			-- Store
			when "01" => 
				we 	<= '1';					
				addr 	<= data(5 downto 0);							
				state <= sstore;
			-- ...
		end case;						
	when sstore =>
		-- write to memory, data is ready next clock								
		data 	<= reg;
		state <= sfetch;
	when others => null;
end case;

data <= reg;