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Altera_Forum's avatar
Altera_Forum
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13 years ago

My First CPU but.. one problem

Hello to all, I completed my first CPU in VHDL, an incredibly satisfying feeling! : D I simulated successfully but I did not understand what it means to a signal colored red in ModelSim: ht...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

There are two possibilities for an 'X' condition in multisim.

1. The signal is uninitialized, therefore the value is unknown and 'X'.

2. The signal is in contention with one side driving a '1' and the other driving a '0'. Multisim can't determine the resulting state and indicates unknown ('X')

You are having issues with contention. When we_synth is set to '1', you must wait one clock for your ram to place the data bus in high impedance before applying data.

It may be a good idea to use a RAM with a data in port and a data out port instead of a single bidirectional data port. This way, you can avoid using 'Z' inside your design (for the RAM interface at least).

Just so you know - the blue areas are times of high impedance. ('Z')