multi case_sentence cause delay

What is delay a lot? Some ns? Multiple clock cycles?

The construct involves combinational logic according to the complexity of the case decoder and the expression itself. But it's unlikely to accumulate more than a few ns logic delay.

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Is that the problem of case inside case ???

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Not particularly.

But when I revise the code,like:

case({first_c,second_c})

{3'd7,3'd7}:expression..

{3'd7,3'd6}:expression..

endcase

the Fmax turns out increased almost10M！that's why I guess the "case inside case"cause to decrease the fmax.（my clk is 250M）

250 MHz is fast enough that one or two LEs in a logic chain play a role. This answers my first question. The difference between 250 and 260 MHz isn't more than 0.15 ns delay, rather a result of different routing than a full LE delay step.

My primary assumption is, that equivalent logic synthesizes to the same gate level netlist. Thus I also assume, that your two variants aren't logically equivalent, but it's most likely not a matter of nested case constructs.

If the constructs are equivalent can't be seen from one or two lines of code.

thanks,FvM!

as a matter of fact,the 2 variants are equivalent,both 3 bits.

I trial and error some times,the outcome is the same.

code as follows the fmax is low.(clk=250M)

case(first_c)
3'd7:case(second_c)
          3'd7:express..
          3'd6:......
          3'd5:......
          3'd4:
          3'd3:
          3'd2:
          3'd1:
          3'd0:
       endcase
3'd6:case(second_c)
          3'd7:express..
          3'd6:......
          3'd5:......
          3'd4:
          3'd3:
          3'd2:
          3'd1:
          3'd0:
          endcase
3'd5:case(second_c)
          3'd7:express..
          3'd6:......
          3'd5:......
          3'd4:
          3'd3:
          3'd2:
          3'd1:
          3'd0:
          endcase
3'd4:case(second_c)
          3'd7:express..
          3'd6:......
          3'd5:......
          3'd4:
          3'd3:
          3'd2:
          3'd1:
          3'd0:
          endcase
3'd3:case(second_c)
          3'd7:express..
          3'd6:......
          3'd5:......
          3'd4:
          3'd3:
          3'd2:
          3'd1:
          3'd0:
          endcase
3'd2:case(second_c)
          3'd7:express..
          3'd6:......
          3'd5:......
          3'd4:
          3'd3:
          3'd2:
          3'd1:
          3'd0:
          endcase
3'd1:case(second_c)
          3'd7:express..
          3'd6:......
          3'd5:......
          3'd4:
          3'd3:
          3'd2:
          3'd1:
          3'd0:
          endcase
3'd0:case(second_c)
          3'd7:express..
          3'd6:......
          3'd5:......
          3'd4:
          3'd3:
          3'd2:
          3'd1:
          3'd0:
          endcase
endcase

codes as follows increases the fmax

case({first_c,second_c})
          {3'd7,3'd7}:expression..
          {3'd7,3'd6}:expression..
          .......
endcase

the other correlative logic is the same.