Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributormulti case_sentence cause delay
Hi when I write the verilog code,like:
case(first_c)
3'd7:case(second_c)
3'd7:express..
3'd6:......
3'd5:......
3'd4:
3'd3:
...
Altera_ForumHonored Contributor
Honored ContributorBut when I revise the code,like:
case({first_c,second_c}) {3'd7,3'd7}:expression.. {3'd7,3'd6}:expression.. endcase the Fmax turns out increased almost10M！that's why I guess the "case inside case"cause to decrease the fmax.（my clk is 250M）
