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Altera_Forum
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14 years ago

multi case_sentence cause delay

Hi when I write the verilog code,like: case(first_c) 3'd7:case(second_c) 3'd7:express.. 3'd6:...... 3'd5:...... 3'd4: 3'd3: ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

What is delay a lot? Some ns? Multiple clock cycles?

The construct involves combinational logic according to the complexity of the case decoder and the expression itself. But it's unlikely to accumulate more than a few ns logic delay.

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Is that the problem of case inside case ???

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Not particularly.