Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributormulti case_sentence cause delay
Hi when I write the verilog code,like:
case(first_c)
3'd7:case(second_c)
3'd7:express..
3'd6:......
3'd5:......
3'd4:
3'd3:
...
Altera_ForumHonored Contributor
Honored ContributorWhat is delay a lot? Some ns? Multiple clock cycles?
The construct involves combinational logic according to the complexity of the case decoder and the expression itself. But it's unlikely to accumulate more than a few ns logic delay. --- Quote Start --- Is that the problem of case inside case ??? --- Quote End --- Not particularly.
