Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributormulti case_sentence cause delay
Hi when I write the verilog code,like:
case(first_c)
3'd7:case(second_c)
3'd7:express..
3'd6:......
3'd5:......
3'd4:
3'd3:
...
Altera_ForumHonored Contributor
Honored Contributor250 MHz is fast enough that one or two LEs in a logic chain play a role. This answers my first question. The difference between 250 and 260 MHz isn't more than 0.15 ns delay, rather a result of different routing than a full LE delay step.
My primary assumption is, that equivalent logic synthesizes to the same gate level netlist. Thus I also assume, that your two variants aren't logically equivalent, but it's most likely not a matter of nested case constructs. If the constructs are equivalent can't be seen from one or two lines of code.
