Forum Discussion
Occasional ContributorModifying the PCIe DMA transfer example design for Arria 10 device.
Hello,
I have a modified version of the PCIe DMA transfer example design (mentioned in the Chapter 7 of attached user manual). As a modification to the example design, I added a custom generated data generator IP and an Avalon FIFO Memory Intel IP to the existing DMA transfer example design {Platform designer screenshot is attached as DMA_modified_part1.PNG and DMA_modified_part2.PNG} . My aim is to continuously generate data (bit stream) in the FPGA using a data generator custom IP (generated from the user Verilog code) and pass it through a FIFO to the DDR4 memory, and then do a DMA transfer though the PCIe to the host computer.
Basically, a continuous DMA read (just read) from the data saved in the FPGA DDR4 memory. After compilation without any error and programming into the FPGA, I am not able to read data using the modified API code(modification I meant, disabling the DMA write API in the API code) on the host computer from the DDR4 memory. As I am trying to debug, I appreciate your comments regarding the configurations I used, and I have the following questions:
1. I would like to make sure that the signals and interfaces that I have used to connect the Avalon FIFO Memory Intel IP to the PCIe DMA example design is correct (please see the attached screenshots). This IP have an input type of Avalon Streaming Sink and Output type of Avalon Memory Map Read. Do you have any comment regarding this selection of the configuration I used?
2. My data generator custom IP is designed to generate bit stream at a rate and runs with the same clock and reset as PCIe DMA Intel IP (In Platform Designer it’s named as DUT). Also, the custom IP have two exported inputs that connects to the two switches of the FPGA (to start and end to data generation respectively). To connect with the Avalon Streaming Sink of the Avalon FIFO Memory Intel IP, the custom data generator IP has an Avalon Streaming Source. Do you have any comments on sharing the reset signal from DUT with the data generator custom IP?
I am working in Arria 10 GX device (10AX115N2F45E1SG) and my host computer is based on windows 10. And I am using Quartus Prime Pro 18.4 version.
Thank you.
15 Replies
AdzimZM_AlteraRegular Contributor
Hi Sijith,
I have sent an email to you. Please let me know in case you are not receiving it.
I am thinking that the memory address should also specified whenever you want to perform transaction into the memory.
I may suggest you to add address parameter as well.
Is there any way that you can confirm the data is successfully written into the memory?
It's will be great to have that as well.
Another thing is have you ever tested the design in simulation mode?
Regards,
Adzim
- AdzimZM_Altera
Hi Sijith,
Thank you for your feedback on my question.
I have checked the data_gen code and it's look like have a variable on data_valid. I am not sure why the data and address are not presented here.
There is data parameter in the code but it's not assign to any number.
I guess this code only allow the DMA to get data_valid?
Where is the data and address been generated and write into DDR?
Sorry if I need more help to explain in this section.
If you want to sent the code directly to me, please let me know because I can reach out to you through Private Message or email.
Regards,
Adzim
SijithHi Adzim,
I suspect I attached a corrupted Verilog file with last message, sorry for that. I really would like to send the code directly to you. It would be great if you could reach-out me though email or private message.
Also I would like to remind you that in my design, the data generated by the data_gen should flow to the DDR4 memory element through FIFO component (here, I have used an Avalon memory FIFO IP with streaming sink input and Avalon MM slave output. In Platform Designer system, the Avalon streaming source from the data_gen interfaces with the Avalon streaming sink of FIFO, and the Avalon MM slave interface of FIFO output connected to the PCIe DMA transfer example design (design provided by Terasic) as seen in screenshots DMA_modified_part2.PNG and DMA_modified_part1.PNG attached above). I am just curious that in this case, do we need to specify the any memory address in my data_gen Verilog code?. Please let me know if you have further questions. Thank you very much.
- AdzimZM_Altera
Hi Sijith,
I will assist you on this issue but focusing on EMIF area.
Need your help to confirm the PCIE example design is tested and worked before it's modified?
The issue is you are not able to read from the memory, is that means there is no data in the memory or any issue you are observing?
The data from data generator needs to be written into the DDR4 memory first right? Then the DMA can read it?
-Adzim
- Sijith
Hi,
Thank you very much for roping in to help me.
1. The PCIe example design was tested and worked fine ( I followed the method explained in the chapter 7 of DE5a-NET-DDR4 manual. I did this using the API code given by Terasic CD/Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4 (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=228&No=1108&PartNo=4#contents). I could verify the read-back of data from the host computer)
2. Yup the issue is I could not read data from memory.
To just DMA read data from the DDR4 (as we don't need any data generation from host computer in our project (what we need is data generated in the FPGA itself), I commented out the DMA write portion of the API C++ code in CD/Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4/PCIE_DDR4/PCIE_DDR4.sln) . When executing the PCIE_DDR4.exe command line to run option [4] DMA DDR4-A Sodium Memory Test, I am getting a value ffffffff (in hex option of printf()). Selecting option [5] DMA DDR4-B Sodium Memory Test also gives same result. A screenshot Capture(2).PNG is attached (in which we can see a random value).
I have assigned the FPGA switch (SW1) to start and stop data generation for my custom IP. So changing the switch position does not seems to have an effect in the execution of DMA read at the host computer.
3. Yes. The data from the custom data generator (I wrote a Verilog code for this) should write it to the DDR4 memory first, then the DMA read API is suppose to read it from the host computer through the PCIe link.
I am attaching a zip folder "ModifiedDesign.zip" contains the modified Platform Designer file (.qsys file), Quartus Project File (.qpf), the data generator Verilog file (used for the custom IP generation) and the API C++ file, incase you would like to have a look in it. Also attaching the factory default files .qsys, .qpf and API of the example design in a zip folder "ExampleDesign.zip" for the sake of comparison.
Let me know if you have any further questions.
FYI: I am using Quartus Prime Pro 18.1 version.
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