Occasional Contributor
Regular ContributorHi Sijith,
I will assist you on this issue but focusing on EMIF area.
Need your help to confirm the PCIE example design is tested and worked before it's modified?
The issue is you are not able to read from the memory, is that means there is no data in the memory or any issue you are observing?
The data from data generator needs to be written into the DDR4 memory first right? Then the DMA can read it?
-Adzim
Occasional ContributorHi,
Thank you very much for roping in to help me.
1. The PCIe example design was tested and worked fine ( I followed the method explained in the chapter 7 of DE5a-NET-DDR4 manual. I did this using the API code given by Terasic CD/Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4 (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=228&No=1108&PartNo=4#contents). I could verify the read-back of data from the host computer)
2. Yup the issue is I could not read data from memory.
To just DMA read data from the DDR4 (as we don't need any data generation from host computer in our project (what we need is data generated in the FPGA itself), I commented out the DMA write portion of the API C++ code in CD/Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4/PCIE_DDR4/PCIE_DDR4.sln) . When executing the PCIE_DDR4.exe command line to run option [4] DMA DDR4-A Sodium Memory Test, I am getting a value ffffffff (in hex option of printf()). Selecting option [5] DMA DDR4-B Sodium Memory Test also gives same result. A screenshot Capture(2).PNG is attached (in which we can see a random value).
I have assigned the FPGA switch (SW1) to start and stop data generation for my custom IP. So changing the switch position does not seems to have an effect in the execution of DMA read at the host computer.
3. Yes. The data from the custom data generator (I wrote a Verilog code for this) should write it to the DDR4 memory first, then the DMA read API is suppose to read it from the host computer through the PCIe link.
I am attaching a zip folder "ModifiedDesign.zip" contains the modified Platform Designer file (.qsys file), Quartus Project File (.qpf), the data generator Verilog file (used for the custom IP generation) and the API C++ file, incase you would like to have a look in it. Also attaching the factory default files .qsys, .qpf and API of the example design in a zip folder "ExampleDesign.zip" for the sake of comparison.
Let me know if you have any further questions.
FYI: I am using Quartus Prime Pro 18.1 version.
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