Occasional Contributor
Regular ContributorHi Sijith,
Thank you for your feedback on my question.
I have checked the data_gen code and it's look like have a variable on data_valid. I am not sure why the data and address are not presented here.
There is data parameter in the code but it's not assign to any number.
I guess this code only allow the DMA to get data_valid?
Where is the data and address been generated and write into DDR?
Sorry if I need more help to explain in this section.
If you want to sent the code directly to me, please let me know because I can reach out to you through Private Message or email.
Regards,
Adzim
Occasional ContributorHi Adzim,
I suspect I attached a corrupted Verilog file with last message, sorry for that. I really would like to send the code directly to you. It would be great if you could reach-out me though email or private message.
Also I would like to remind you that in my design, the data generated by the data_gen should flow to the DDR4 memory element through FIFO component (here, I have used an Avalon memory FIFO IP with streaming sink input and Avalon MM slave output. In Platform Designer system, the Avalon streaming source from the data_gen interfaces with the Avalon streaming sink of FIFO, and the Avalon MM slave interface of FIFO output connected to the PCIe DMA transfer example design (design provided by Terasic) as seen in screenshots DMA_modified_part2.PNG and DMA_modified_part1.PNG attached above). I am just curious that in this case, do we need to specify the any memory address in my data_gen Verilog code?. Please let me know if you have further questions. Thank you very much.
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