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Altera_Forum's avatar
Altera_Forum
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14 years ago

ModelSim with VHDL 2008

Peace be upon you;

I am using Quartus II 11.1, ModelSim 10.c (x64), I am used to design my files on Quartus and simulate it on ModelSim using VHDL 2002;

Then I had to move to VHDL 2008 due to some syntax problems, it worked nice with Quartus, but when I try to simulate it on ModelSim, Its compiler can't compile it even if I try to force it to use VHDL 2008, Procedure is as follows:

*Design & Compile on Quartus.

*Run RTL Simulation. --ModelSim is summoned.

*Modelsim's default compilation is VHDL 2002 so it gets errors.

*Adjust ModelSim's compiler options to VHDL 2008.

*Nothing happens.

Thanks in advance.

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    the altera version is the limited version of modelsim, provided by altera, and is released every so often (probably about every 6 months)

    The PE version requires a separate licence. But it allows mixed code simulations.

    The SE version is even more expensive but has a 64 bit version for increased memory requirements and a lot of other gubbins people dont use.

    So I guess you're stuck until Altera release a new Modelsim ASE.

    Could you actually explain what you are trying to do? Could you not replace the generic with a constant in a package?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I am trying to create a generic register file

    { Generic Width

    Generic number of registers

    Generic number of Read/Write Ports }

    I could achieve this by using a 2D array : Type 2D_Array (Natural Range<>, Natural Range <>) of STD_LOGIC ;

    But this way caused trouble when I use it because when I try to use the register file as a component, I have to deal with its Read/Write Ports as a 2D array, so it would be a lot easier to have an array of STD_LOGIC_VECTOR instead.

    A constant in a package restricts the use of the register file as I use it a lot with variable parameters.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    how about just creating a type that covers the worst case?

    eg:

    type reg_array_t is array(natural range <>) of std_logic_vector(31 downto 0);

    then leave anything you dont use disconnected. It will get synthesised away.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Well, I can't do so, we are creating a very customized micro Processor, I can't reserve registers that I don't use.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Well I think the only options are:

    1. Do it without being able to simulate that part of the design.

    2. Get a modelsim PE licence

    3. Get another simulator (like Active HDL)

    4. Use a large std_logic_vector array, and break it up using functions, like dave said.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I tried to change the compiling options and the following message:

    "Unable to replace existing ini file (modelsim.ini). File can not be renamed."

    which makes sense if you didn't pay the US$945 version.

    Good luck
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    I tried to change the compiling options and the following message:

    "Unable to replace existing ini file (modelsim.ini). File can not be renamed."

    which makes sense if you didn't pay the US$945 version.

    --- Quote End ---

    I think you'll find that you first need to right-click on the file and change it from read-only :)

    Cheers,

    Dave