ModelSim with VHDL 2008

I am trying to create a generic register file

{ Generic Width

Generic number of registers

Generic number of Read/Write Ports }

I could achieve this by using a 2D array : Type 2D_Array (Natural Range<>, Natural Range <>) of STD_LOGIC ;

But this way caused trouble when I use it because when I try to use the register file as a component, I have to deal with its Read/Write Ports as a 2D array, so it would be a lot easier to have an array of STD_LOGIC_VECTOR instead.

A constant in a package restricts the use of the register file as I use it a lot with variable parameters.