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Altera_Forum
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14 years ago

ModelSim with VHDL 2008

Peace be upon you; I am using Quartus II 11.1, ModelSim 10.c (x64), I am used to design my files on Quartus and simulate it on ModelSim using VHDL 2002; Then I had to move to VHDL 2008 due to so...
Altera_Forum's avatar
Altera_Forum
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14 years ago

how about just creating a type that covers the worst case?

eg:

type reg_array_t is array(natural range <>) of std_logic_vector(31 downto 0);

then leave anything you dont use disconnected. It will get synthesised away.