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Altera_Forum
Honored Contributor
Honored ContributorModelSim with VHDL 2008
Peace be upon you; I am using Quartus II 11.1, ModelSim 10.c (x64), I am used to design my files on Quartus and simulate it on ModelSim using VHDL 2002; Then I had to move to VHDL 2008 due to so...
Altera_ForumHonored Contributor
Honored ContributorWell I think the only options are:
1. Do it without being able to simulate that part of the design. 2. Get a modelsim PE licence 3. Get another simulator (like Active HDL) 4. Use a large std_logic_vector array, and break it up using functions, like dave said.
