Forum Discussion
Honored Contributormodel a buffer in VHDL
Hi,
Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated from the register for the next 2 second. Can anyone help me..Thanks17 Replies
Altera_ForumAs I told you your error is because clk is port name of component while the top level name is clock (not clk).
Your work is just registers and you can equally just infer them i.e. clocked process saying output <= input (clock itself should not be registered). But for your original post of 2 sec delay, you are not doing that yet...- Altera_Forum
Actually i try to produce output of out1 after delay time of 1ns. I use components of register and buffer in a package. The main file is haar.vhd which i have write at the last post. Another file is bufgs.vhd and reg.vhd that describe the component's operation respectively. But i didn't include it here.
I don't know where is my mistake cause i try debug many time..By the way kaz, thanks for response. - Altera_Forum
Just change name from clk to clock in the wiring of your 2nd instantiation.
But still i am not sure what your doing. - Altera_Forum
This is my code;
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY haar IS PORT ( clock : IN bit; -- Inputs in1 : IN integer RANGE -127 TO 127; --Outputs out1 : OUT integer RANGE -127 TO 127 ); END haar; ARCHITECTURE haar OF haar IS COMPONENT bufgs PORT ( i : IN bit; clk : IN bit; o : OUT bit ); END COMPONENT; COMPONENT reg PORT ( input : IN integer RANGE -127 TO 127; clk : IN bit; output : OUT integer RANGE -127 TO 127 ); END COMPONENT; BEGIN xbufgs : bufgs PORT MAP ( clock, clk); -------Input to Register ------- r1: reg PORT MAP ( in1, clk, out1 ); END haar; I use components of register and buffer in the code. But, this error occurred when i compile this code: Error (10482): VHDL error at haar.vhd(35): object "clk" is used but not declared. Can you help me why this error is occurred.Thanks - Altera_Forum
In that case you can delay in (n) units of your clock period using a pipe of registers (shift) or better for long delays use ram. But 2 seconds of delay could be too much of a burden on ram depth if your clock is fast and I can see it justified for deep interleaving algorithms. If your clock is slowed e.g. by division then you may need smaller ram or even use just registers enabled by a slow clken signal that results in 2 seconds time.
- Altera_Forum
Dear kaz,
I want to use a buffer component in my VHDL code. I want to use the buffer as a time delay for my input and output signal. Thanks for reply - Altera_Forum
what do you mean by buffer? You need to elaborate more.
Buffer is used according to several contexts. 1) I know digitally minded folks use buffer to mean storing incoming streams and then releasing it under control. This could be a block of ram or fifo or even a pipe of registers. 2) analogue folks use it for buffering voltage or current sources and produce zero or so internal impedance. 3) vhdl standads suggest buffer ports meaning output port that can be read but thankfully nobody uses this port except students and professors. 4) buffer zone is also used in traffic, wars, and in fact any form of flow
