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Altera_Forum
Honored Contributor
Honored Contributormodel a buffer in VHDL
Hi, Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated ...
Altera_ForumHonored Contributor
Honored ContributorActually i try to produce output of out1 after delay time of 1ns. I use components of register and buffer in a package. The main file is haar.vhd which i have write at the last post. Another file is bufgs.vhd and reg.vhd that describe the component's operation respectively. But i didn't include it here.
I don't know where is my mistake cause i try debug many time..By the way kaz, thanks for response.
