model a buffer in VHDL

This is my code;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY haar IS

PORT (

clock : IN bit;

-- Inputs

in1 : IN integer RANGE -127 TO 127;

--Outputs

out1 : OUT integer RANGE -127 TO 127

);

END haar;

ARCHITECTURE haar OF haar IS

COMPONENT bufgs

PORT (

i : IN bit;

clk : IN bit;

o : OUT bit

);

END COMPONENT;

COMPONENT reg

PORT (

input : IN integer RANGE -127 TO 127;

clk : IN bit;

output : OUT integer RANGE -127 TO 127

);

END COMPONENT;

BEGIN

xbufgs : bufgs

PORT MAP (

clock, clk);

-------Input to Register -------

r1: reg

PORT MAP ( in1, clk, out1 );

END haar;

I use components of register and buffer in the code. But, this error occurred when i compile this code:

Error (10482): VHDL error at haar.vhd(35): object "clk" is used but not declared.

Can you help me why this error is occurred.Thanks