model a buffer in VHDL

In that case you can delay in (n) units of your clock period using a pipe of registers (shift) or better for long delays use ram. But 2 seconds of delay could be too much of a burden on ram depth if your clock is fast and I can see it justified for deep interleaving algorithms. If your clock is slowed e.g. by division then you may need smaller ram or even use just registers enabled by a slow clken signal that results in 2 seconds time.