Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributormodel a buffer in VHDL
Hi, Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated ...
Altera_ForumHonored Contributor
Honored ContributorAs I told you your error is because clk is port name of component while the top level name is clock (not clk).
Your work is just registers and you can equally just infer them i.e. clocked process saying output <= input (clock itself should not be registered). But for your original post of 2 sec delay, you are not doing that yet...
