Altera_Forum
Honored Contributor
9 years agomin/max trace delays
Hi,
could someone explain how to calculate min/max trace delays for clock and data lines? I would like to constrain FPGA inputs. I am using source synchronous DDR interface and i want to constrain them with formulas found on "AN 433: Constraining and AnalyzingSource-Synchronous Interfaces": input maximum delay value = maximum trace delay for data + unit interval - tsu of external device – minimum trace delay for clock
input minimum delay value = minimum trace delay for data + th of external device – maximum trace delay for clock
But i didint find any info on how to calculate trace delays of PCB.