Forum Discussion
Honored Contributormin/max trace delays
Hi,
could someone explain how to calculate min/max trace delays for clock and data lines? I would like to constrain FPGA inputs. I am using source synchronous DDR interface and i want to constrain them with formulas found on "AN 433: Constraining and AnalyzingSource-Synchronous Interfaces": input maximum delay value = maximum trace delay for data + unit interval - tsu of external device – minimum trace delay for clock
input minimum delay value = minimum trace delay for data + th of external device – maximum trace delay for clock
But i didint find any info on how to calculate trace delays of PCB.
6 Replies
Altera_ForumAnyone?
Does maximum trace delay for data equals to propagation time of longest data line and minimum trace delay for data equals to propagation time of shortest data line? What about minimum trace delay for clock and maximum trace delay for clock?- Altera_Forum
The velocity of propagation (trace delay) is dominated by the dielectric constant of the PCB material. Assuming a standard FR4 PCB, you won't go far wrong with 165ps per inch. The tolerance on that is down to PCB process, which won't change that figure very dramatically. So, the "minimum trace delay for clock and maximum trace delay for clock" are not going to be very different from each other - if at all.
Regards, Alex - Altera_Forum
Thanks Alex,
so this means that: maximum trace delay for data = longest data trace length * 165ps minimum trace delay for data = shortest data trace length * 165ps min/max trace delay for clock = clock trace length *165ps - Altera_Forum
That looks about right.
Cheers, Alex - Altera_Forum
How the trace is routed (microstrip vs. stripline) makes a pretty significant difference in prop delay. Rules of thumb are 150ps/in for microstrip and 180ps/in for stripline. 165ps/in is the average of those two, which I'm sure Alex knows. If you really need precise numbers then you should account for this, and for your actual stackup and dielectric, etc. Most PCB layout programs these days will give you trace delays based on the actual routing of the traces. Talk to your layout person.
- Altera_Forum
Thanks a_x_h_75 and rsefton for your answers.
I am curious if other FPGA designers actually take care of those delays with that much precision or calculations provided by Alex is more than enough?
