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Altera_Forum's avatar
Altera_Forum
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10 years ago

min/max trace delays

Hi, could someone explain how to calculate min/max trace delays for clock and data lines? I would like to constrain FPGA inputs. I am using source synchronous DDR interface and i want...
Altera_Forum's avatar
Altera_Forum
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9 years ago

How the trace is routed (microstrip vs. stripline) makes a pretty significant difference in prop delay. Rules of thumb are 150ps/in for microstrip and 180ps/in for stripline. 165ps/in is the average of those two, which I'm sure Alex knows. If you really need precise numbers then you should account for this, and for your actual stackup and dielectric, etc. Most PCB layout programs these days will give you trace delays based on the actual routing of the traces. Talk to your layout person.