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Altera_Forum's avatar
Altera_Forum
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10 years ago

min/max trace delays

Hi, could someone explain how to calculate min/max trace delays for clock and data lines? I would like to constrain FPGA inputs. I am using source synchronous DDR interface and i want...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks Alex,

so this means that:

maximum trace delay for data = longest data trace length * 165ps

minimum trace delay for data = shortest data trace length * 165ps

min/max trace delay for clock = clock trace length *165ps