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Altera_Forum
Honored Contributor
Honored Contributormin/max trace delays
Hi, could someone explain how to calculate min/max trace delays for clock and data lines? I would like to constrain FPGA inputs. I am using source synchronous DDR interface and i want...
Altera_ForumHonored Contributor
Honored ContributorAnyone?
Does maximum trace delay for data equals to propagation time of longest data line and minimum trace delay for data equals to propagation time of shortest data line? What about minimum trace delay for clock and maximum trace delay for clock?
