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Altera_Forum
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9 years ago

min/max trace delays

Hi, could someone explain how to calculate min/max trace delays for clock and data lines? I would like to constrain FPGA inputs. I am using source synchronous DDR interface and i want...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

The velocity of propagation (trace delay) is dominated by the dielectric constant of the PCB material. Assuming a standard FR4 PCB, you won't go far wrong with 165ps per inch. The tolerance on that is down to PCB process, which won't change that figure very dramatically. So, the "minimum trace delay for clock and maximum trace delay for clock" are not going to be very different from each other - if at all.

Regards,

Alex