Minimum pulse width violation for altsyncram

Hi, all,

During timing analisys I get unexpected minimum pulse width violation for clock signal in very simple project with altsyncram. I am using TimeQuest Timing Analyzer in Quartus II v12 and compile for Cyclone II.

Device has singleport altsyncram, input pins, registers for them, output pin and clock control block. The last is used to guarantee the proper global clock for memory. As everything is synced on front edge of clock, I wouldn't expect low or high pulse width violation for clock.

Here is my sdc file:

create_clock -period 220MHz -waveform {0.00 2.27} -name {clk} 

For CycloneII memory blocks I would expect fmax not much less, than 250 MHz, but actually I get less than 200MHz for EP2C3F672C6.

Here is message about frequency that I get:

| Fmax | Restricted Fmax | Clock Name | Note

| 316.06 MHz | 199.96 | clk | limit due to high minimum pulse width violation (tch)

Types of violation in minimum pulse width report are both high pulse width and low pulse width.

Here are some targets of violation from minimum pulse width report:

--- Quote Start ---

sram_megaf:inst|altsyncram:altsyncram_component|altsyncram_oub1:auto_generated|q_a[0]

sram_megaf:inst|altsyncram:altsyncram_component|altsyncram_oub1:auto_generated|q_a[1]

<..>

sram_megaf:inst|altsyncram:altsyncram_component|altsyncram_oub1:auto_generated|q_a[7]

sram_megaf:inst|altsyncram:altsyncram_component|altsyncram_oub1:auto_generated|ram_block1a0~porta_address_reg0

<..>

sram_megaf:inst|altsyncram:altsyncram_component|altsyncram_oub1:auto_generated|ram_block1a0~porta_address_reg4

sram_megaf:inst|altsyncram:altsyncram_component|altsyncram_oub1:auto_generated|ram_block1a0~porta_datain_reg0

<..>

sram_megaf:inst|altsyncram:altsyncram_component|altsyncram_oub1:auto_generated|ram_block1a0~porta_datain_reg7

--- Quote End ---

Is this a problem of not fast enough device or is it something else?

Some authors here previously had similar problem. Some solutions were about synchronizing memory interface, but it wouldn't help in my case as memory inputs are already fed by registers.

I would appreciate any help!

Sincerely,

Olga