Minimum pulse width violation for altsyncram

I think of Minimum Pulse Width violations as pure Fmax limitations for dedicated hardware. For example, if I created a design with just two FFs and they were put right next to each other, normal static timing analysis might evaluate an 800ps data delay, 200ps of skew, and say the device can run at 1GHz. Although the numbers used are correct, the clock tree won't toggle that fast, and so MPW comes in and says it needs to run slower. Dedicated blocks like the RAMs also have MPWs. Now, it may be split into a low and high time requirement rather than a single Fmax value, but the net result is the same. (Perhaps the RAM does something internally on the falling edge). In the end, I don't think it's designed to run that fast.