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Altera_Forum
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13 years ago

Minimum pulse width violation for altsyncram

Hi, all, During timing analisys I get unexpected minimum pulse width violation for clock signal in very simple project with altsyncram. I am using TimeQuest Timing Analyzer in Quartus II v12 an...
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Altera_Forum
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13 years ago

Rysc, thank you for the link! I guess number I used for reference was not exact. Cyclone II device handbook on Altera official site - this is where I found 250MHz as maximum performance of embedded memory.

Actually, I showed results I got for EP2C3F672C6 which is 6 speed grade. So I am still not sure how to interpret data from timing analysis. The biggest question is why high and low pulse width make the limitation, since all elements in device are synchronized only on front edge.