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Altera_Forum's avatar
Altera_Forum
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10 years ago

Memory works in simulation, but not on HW?

Hello guys, I used the megafunction wizard to create 1-Port RAM. Then I managed to make the input and output bus as a single bi-directional bus. So the top level entity is :

entity SRAM is port

(

OE : in std_logic;

WR : in std_logic;

Data_Bus : inout std_logic_vector (7 downto 0);

Address_Bus: in std_logic_vector (7 downto 0) ;

clk : in std_logic

);

Now in simulation (Timing and functional) , everything is working ok. I can write and read properly from the RAM after providing the clock. But now I assigned pins for the IOs , and tried to use it with microcontroller, but it is not working . I have not used any dedicated IOs and the IO bank is powered .

What can the problem be ?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If I understand correctly you use an external (no NIOS etc.) microcontroller. Do you synchronise the clocks and data or how do you interface this?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Well , it works on the rising edge of the clock, so its very simple, u just activate WR or OE for read or write , then put the address and at the first coming rising edge, data is either sampled for write , or output for read. I'm using normal microcontroller, and I even wait for multiple clocks before i sample the data. Like I said it is working fine in simulation. See the attachment of the simulation results.

    Thx in advance man.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Just a couple of questions/statements that might help:

    Have you simulated what happens if both OE and WR are low and high?

    Also, sometimes, IO is active-low which means you have to invert the signal.

    Are you sure the microcontroller code is correct? Can you check with a scope or LEDs?

    [edit]Oh, and are you sure about your connections? All wires connected to the correct pins?[/edit]
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The signals are active low, it 's my own design, and of course the WR and OE can not be active at the same time (Data contention hazards might occur). I'm sure they can not be active at the same time as im using advanced microcontroller from ST and it has memory controller as a peripheral, so WR and OE can not be active at the same time. I will recheck the IOs mapping , and will change the whole IOs and see how things go .