Honored ContributorHi. Imagine I have the following schematic in Quartus II
http://www.alteraforum.com/forum/attachment.php?attachmentid=11037&stc=1 How can I measure the time elapsed from the instant the clock signal is applied to module LCG to its output data update?
Honored ContributorNo - and why would you care?
With a synchronous design, you shouldnt care about path delays like this, especially not on a clock. You just know that data will always arrive before the clock. If the timing analyser fails for a given path, you need to reduce the logic on that path (break it up with registers), NOT skew the clock on the failing path. If it was even possible, it would easily lead to chaos!Honored ContributorHi,
"You just know that data will always arrive before the clock" What do you mean with that? Let's say that the LCG module is implemented in some FPGA zone and requires 5 clock cycles to complete its operation (honestly I don't have any clue on the amount of time it requires). Moreover probably there are also some data delay imposed from the multiplexer. I must seek to match the actual generated register address with the correct dataword provided by the LCG. The problem is that I believe that the fitter process does not respect the actual schematic design... I'm a little lost!Honored ContributorIf the data will arrive several clocks later, you will need some sideband "valid" signal generated from the LCG module, which you can connect to the wren port on the ram, or keep as a sideband signal around the ram.
This is not a problem of timing. THis is a problem of the design.
