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Altera_Forum
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10 years ago

Measuring processing time

Hi. Imagine I have the following schematic in Quartus II http://www.alteraforum.com/forum/attachment.php?attachmentid=11037&stc=1 How can I measure the time elapsed from the instant the clock s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi,

"You just know that data will always arrive before the clock" What do you mean with that? Let's say that the LCG module is implemented in some FPGA zone and requires 5 clock cycles to complete its operation (honestly I don't have any clue on the amount of time it requires). Moreover probably there are also some data delay imposed from the multiplexer. I must seek to match the actual generated register address with the correct dataword provided by the LCG. The problem is that I believe that the fitter process does not respect the actual schematic design... I'm a little lost!