Me and my simple questions: Can I do this in FPGA?

--- Quote Start ---

Why do you want to use bcd? That makes things very complicated and use a lot of resources. Why not just work in binary like every other language? You can easily do arithmatic in vhdl with the IEEE.numeric_std library

A <= b + (c*d);

--- Quote End ---

Very interesting, so you suggest me to convert the input from decimal to entirely Binary, process everything inside and then to convert back to decimal?

Tricky now that you mentioned, I'm not that sure that the input should be decimal, but I'm quite sure that in the end I have to reflect somehow results in decimal (for showing purpose).

This is for a project in my course, I'm working with a hypothetical FPGA system that read a black and white picture in which every pixel has a different pixel intensity ranging from 0 to 99, those values are loaded into a list, that I have to cluster according to "Membership value" of every pixel into only 3 groups.

Each pixel should be processed by 1 PE to calculate "membership" as shown equation in my OP. (Then, each PE will communicate each other so they can "update" membership, but that's another story).

This equation includes Adding, subtraction, multiply and dividing. One big issue is that factional values (example: 0.0002) are generated in the process, (it also generates real periodic numbers like 0.1416.........., but I will keep them limited to a certain fixed number).

My work doesn't include how to catch the pixel intensity numbers, I will just take the values from a list, so I think you are right, maybe I can consider the list originally in binary, and in the end I cluster them in groups by binary also, without needing decimals ever.

Do you think doing divisions and multiplications of fractional values is any easy or feasible? My intention is to make this as simple as possible. Thanks so much!

--- Quote Start ---

Tricky now that you mentioned, I'm not that sure that the input should be decimal, but I'm quite sure that in the end I have to reflect somehow results in decimal (for showing purpose).

--- Quote End ---

If this is an image then is better to display as gray level or color shades than printing some number other than image is very limited on resolution.

--- Quote Start ---

Do you think doing divisions and multiplications of fractional values is any easy or feasible? My intention is to make this as simple as possible. Thanks so much!

--- Quote End ---

IQ mathematics are possible in FPGA logic as is possible on Integer processor without FP. ALso FP unit can be built on FPGA too..

Again the equation you posted has a lot of coefficients and indexes, if you wish some help please tell us about numbers and range.

Equation in first can be reworked using a negative exponent, this don't free from checking for negative values nor from division by zero. Exponent is fractional too so care must be applied to evaluate m coefficient can also raise to infinite values.

The board you own has a lot of power on both FPGA and HPS sections, both can handle that equation but for both you must have clean the scope.

From question you are posting I fear you need grasp VHDL before do this job is this right? If so some basic exercises can clean most of your doubt.

VHDL is a complex hardware descriptor language but also a programming and simulation language, it is not simple but not so difficult it just need some hint and patience and you can do everything you think in hardware/software.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11659&stc=1

Sorry, I cant make it size smaller. (weird loading picture sys)

This is the equation more simplified. Exponents are only squares, no need of fractional squares. About ranges, Maximun integer number should be 99 (2 digits) and fractional part .999999 (6 digits), no negative numbers because subtraction is absolute value.

I will consider input and oupt binary so I can work more easily. I have been reading about fractional operations in VHDL, it seems that there are already a library for such, do you know about this?

You dont need to consider binary at all - it doesnt matter what base the number is in - the equation is still the same. All computers, maths programs and everything work in binary - decimal is just a convenient representation for the human brain to understand. Just imagine your inputs are decimal. It will only make a difference for the number of bits required for operation.

If the input range is 0-99, then you need 7 integer bits (0-127). You cannot get exact resolution to make .999999, you need to decide how many fraction 2^n bits you need. 6 fractional bits gives you precision to the nearest 0.015625. 12 bits = 0.00048828125.

But usually you can work backwards - what precision is required at the output? this can give you the precision at the input.

Hey I have found this library for fixed point operations “fixed_float_types.vhdl”, “fixed_generic_pkg.vhdl”, “fixed_generic_pkg-body.vhdl”,

and “fixed_pkg.vhdl”.

I might just declare values directly at binary in integer.decimal format and perform the operations normally with + and *

My question however if this kind of "libraries" are synthesizable and quartus II can work with them without problems. I know for example that the "/" division can be used in quartus II, but it won't synthesize in the FPGA, correct?

The fixed point package is part of the vhdl 2008 language spec. But quartus does not fully support 2008 yet - but David Bishop wrote a '93 compatible version of the fixed_pkg that compiles well with quartus (at least it worked just fine about 6 years ago and I dont see why it would stop working now - I infered rams and multipliers with it just fine). You can download it from here: http://www.vhdl.org/fphdl/

This package doesnt really do anything other than integer arithmetic - it is just holds the numbers in an easier to understand (and modify) format. There is nothing you can do with this package you cannot do with integers (but it takes a little more careful though). The logic created is identical (as fixed point is simply integer arithmatic with an offset).

The "/" function can be used perfectly happily from any library in the FPGA - but it wont be pipelined so it will have a really slow fmax. You'll need to generate an lpm_divide megafunction to get any decent speed out of your design.

PS. in VHDL an integer type has no binary representation directly - it needs to be converted to some binary type (but it will synthesise just fine).

ie.

signal int : integer := 16;

you cannot access individual bits. But you could convert it to an unsigned type:

signal my_uns : unsigned(6 downto 0);

my_uns := to_unsigned(int, my_uns'length);

some_bit <= my_uns(3); -- bit 3 of the my_uns signal

but just so you understand than an integer is just a number, you can also assign it from base 16, base 2 etc:

int := 16#ABCDE#;

int := 2#110100101001#;

--- Quote Start ---

This is the equation more simplified. Exponents are only squares, no need of fractional squares. About ranges, Maximun integer number should be 99 (2 digits) and fractional part .999999 (6 digits), no negative numbers because subtraction is absolute value.

I will consider input and oupt binary so I can work more easily. I have been reading about fractional operations in VHDL, it seems that there are already a library for such, do you know about this?

--- Quote End ---

Sign has no trouble on this equation due exponents are all even number so it can just rewritten with numerator and denominator raised to 4th power and again even so no trouble with sign.

This forever has trouble with denominator of summation, division by zero is not prevented from.

From assumption this is a module i and k parameter are constants across computation so are of no interest on formula.

Calculus is not optimized from VHDL perspective so you have to reduce strength before to sintetyze.

but now how large is image and how uki xi vk vl interact between them? and from where are coming inputs and where are going outputs?

Hint: start do some program in computer language and familiarize with integer fractional number and on scaling fractional to use integers then do a first step of manipulate integers number on FPGA, I think you get a better result than try to build an impossible project from scratch.

I wanted to consult one more thing to you guys, the Soft Core Nios II, would it be more easy to use this CPU for my purpose by programming a custom logic? In that case I'd use C language ,right? so in the end will be more easy?

rromano001 yes, i will start by programming as you said, regarding your questions

but now how large is image :

There is not actual image, I want to use a list of numbers, every number (binary) indicate a pixel intensity, I'm reducing everything to the clustering of a list of numbers, which can be 1000 numbers for example to be grouped in 3 clusters by calculating its membership value and centroids.

This is manage by loading only 1 number to a PE to do the calculation of the equation above. It will produce the first Uki and Vk (centroid), by communicating with the other clones PE it will update Vk and will calculate Uki again, and so on.

So, the difficult part here is to make the PE to perform Subtraction, Adding, Multiplication and Division of fractional numbers.

and how uki xi vk vl interact between them? As is in the equation.

and from where are coming inputs and where are going outputs?

I think I will use the memory of the development board to load a table with the 1000 numbers to be distributed to each PE, and output goes to the neighbor PE to the update, and when it finish to do clustering, it will load the results in memory I guess.