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This is the equation more simplified. Exponents are only squares, no need of fractional squares. About ranges, Maximun integer number should be 99 (2 digits) and fractional part .999999 (6 digits), no negative numbers because subtraction is absolute value.
I will consider input and oupt binary so I can work more easily. I have been reading about fractional operations in VHDL, it seems that there are already a library for such, do you know about this?
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Sign has no trouble on this equation due exponents are all even number so it can just rewritten with numerator and denominator raised to 4th power and again even so no trouble with sign.
This forever has trouble with denominator of summation, division by zero is not prevented from.
From assumption this is a module i and k parameter are constants across computation so are of no interest on formula.
Calculus is not optimized from VHDL perspective so you have to reduce strength before to sintetyze.
but now how large is image and how uki xi vk vl interact between them? and from where are coming inputs and where are going outputs?
Hint: start do some program in computer language and familiarize with integer fractional number and on scaling fractional to use integers then do a first step of manipulate integers number on FPGA, I think you get a better result than try to build an impossible project from scratch.
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