Me and my simple questions: Can I do this in FPGA?

The fixed point package is part of the vhdl 2008 language spec. But quartus does not fully support 2008 yet - but David Bishop wrote a '93 compatible version of the fixed_pkg that compiles well with quartus (at least it worked just fine about 6 years ago and I dont see why it would stop working now - I infered rams and multipliers with it just fine). You can download it from here: http://www.vhdl.org/fphdl/

This package doesnt really do anything other than integer arithmetic - it is just holds the numbers in an easier to understand (and modify) format. There is nothing you can do with this package you cannot do with integers (but it takes a little more careful though). The logic created is identical (as fixed point is simply integer arithmatic with an offset).

The "/" function can be used perfectly happily from any library in the FPGA - but it wont be pipelined so it will have a really slow fmax. You'll need to generate an lpm_divide megafunction to get any decent speed out of your design.

PS. in VHDL an integer type has no binary representation directly - it needs to be converted to some binary type (but it will synthesise just fine).

ie.

signal int : integer := 16;

you cannot access individual bits. But you could convert it to an unsigned type:

signal my_uns : unsigned(6 downto 0);

my_uns := to_unsigned(int, my_uns'length);

some_bit <= my_uns(3); -- bit 3 of the my_uns signal

but just so you understand than an integer is just a number, you can also assign it from base 16, base 2 etc:

int := 16#ABCDE#;

int := 2#110100101001#;