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johnson037's avatar
johnson037
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1 year ago

May I use agilex5 SERDES TX Function and Let the SERDES TX Function Data Rate Lower than 600Mb

Hi :

We have used to use CycloneV FPGA SERDES TX Function to Verify our ASIC Function,

and the SERDES TX Function data rate is only 192Mb, the Quartus IP Mega-Function Wizard

allow this kind of parameter Setting. (use 24Mto192M PLL, Parallel to Serial rate is

Recently we want to migrate our FPGA Verification Environment from CycloneV to

Agilex5, but it seems that the lowest SERDES TX Function for agilex5 is 600Mb.

The IP Generation for Quartus Prime Pro 24.3 do not allow the SERDES TX Function

Parameter Setting (use 24Mto192M PLL, Parallel to Serial rate is 8).

the permitted parameter Setting is use 75Mto 600M PLL, Parallel to Serial rate is 8.

If we still need 192Mb SERDES TX Function on Agilex5 FPGA to Verify out ASIC Function,

what can we do for this limitation of Agilex5 FPGA !?...

Do you have another method to achieve our Goal !?

(192Mb SERDES TX Function)

Sincerely Thanks for the method you offer.

Generic Io

5 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,

    I was primarily thinking of implementing the DDIO logic in FPGA fabric which involves an asynchronous mux in the output. We had also alt_ddio available with previous FPGA families. With Agilex you have GPIO IP in DDIO mode available.



    Regards

    Frank

    • johnson037's avatar
      johnson037
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi Frank :

      Thanks for your Method,

      One More Question is

      " If We use 8bits parellel SERDES TX IP (Lowest Data Rate is 600Mbs), the 8bits Parallel Data Clock is Only 600/8 = 75MHz,

      but the Method you suggested for 192Mbps LVDS Function use DDR IO IP. the Data Clock will be 96MHz"

      Are you Sure that agilex5 FPGA can Support 96MHz Clock Speed after we use Quartus Prime-Pro 24.3 Edition tool to

      Synthesize & Optimization our Digital Design.

      If the Maximum clock Speed can Reach 96Mhz after Quartus Prime-Pro 24.3 Edition tool Synthesize & Optimization our

      Digital Design, I think the 8bits Parallel Data Clock is Only 600/8 = 75MHz will be a better solution, because its clock Rate is

      Only 75Mhz.

      How do you think my opinion !?...

      thanks for your technique opinion.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago
    Hi,
    first I must confess that I don't understand the concept of Agilex 5 (and also Agilex 7 M) SERDES which isn't able to handle commonly used data formats like 8b/10b coded streams or popular data rates natively. It seems to ignore standard application requirements.
    Low data rate SERDES can be always implemented in FPGA fabric without using specific IP. Question is if you need to implement CDR with your serial receiver. I guess not because it's neither available for Cyclone V without specific user logic.

    There's also an option to use >= 600 MBPS SERDES as an oversampling front end for 192 MBPS, but it's probably simpler to implement low speed SERDES directly.

    Regards
    Frank
    • johnson037's avatar
      johnson037
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi Frank :

      thanks for your reply,

      last Mail, you have mentioned that "Low data rate SERDES can be always implemented in FPGA fabric without using specific IP"

      I don't know how to implement your suggestion, because SERDEX TX is Pos/Neg edge clock Double Data Rate transmit

      method.

      Could you offer me some reference Data to let me study how to implement

      "192Mb SERDES TX Function without using specific IP"

      Sincerely thanks for your technical Support.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    96 MHz is SERDES fast clock, slow clock would be 24 MHz for serialization factor 8. 192 MHz data rate is rather low, so you might also consider an implementation without DDIO registers and 192 MHz fast clock. Both should work.

    Please admit that I don't have Agilex 5 support installed in my Quartus Pro tool chain (I'm on 22.4 with my present Arria 10 and Cyclone 10 GX projects), thus I can't check implementation on Agilex 5.

    Actual system clock rate of your design depends on overall topology which I don't know. I expect that it's most likely higher than SERDES slow clock of 24 MHz, so you'll have an elastic buffer between SERDES and system clock domain data stream.

    Regards
    Frank