May I use agilex5 SERDES TX Function and Let the SERDES TX Function Data Rate Lower than 600Mb

Hi Frank :

Thanks for your Method,

One More Question is

" If We use 8bits parellel SERDES TX IP (Lowest Data Rate is 600Mbs), the 8bits Parallel Data Clock is Only 600/8 = 75MHz,

but the Method you suggested for 192Mbps LVDS Function use DDR IO IP. the Data Clock will be 96MHz"

Are you Sure that agilex5 FPGA can Support 96MHz Clock Speed after we use Quartus Prime-Pro 24.3 Edition tool to

Synthesize & Optimization our Digital Design.

If the Maximum clock Speed can Reach 96Mhz after Quartus Prime-Pro 24.3 Edition tool Synthesize & Optimization our

Digital Design, I think the 8bits Parallel Data Clock is Only 600/8 = 75MHz will be a better solution, because its clock Rate is

Only 75Mhz.

How do you think my opinion !?...

thanks for your technique opinion.