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johnson037's avatar
johnson037
Icon for New Contributor rankNew Contributor
1 year ago

May I use agilex5 SERDES TX Function and Let the SERDES TX Function Data Rate Lower than 600Mb

Hi : We have used to use CycloneV FPGA SERDES TX Function to Verify our ASIC Function, and the SERDES TX Function data rate is only 192Mb, the Quartus IP Mega-Function Wiza...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,

I was primarily thinking of implementing the DDIO logic in FPGA fabric which involves an asynchronous mux in the output. We had also alt_ddio available with previous FPGA families. With Agilex you have GPIO IP in DDIO mode available.



Regards

Frank