May I use agilex5 SERDES TX Function and Let the SERDES TX Function Data Rate Lower than 600Mb

Hi,
96 MHz is SERDES fast clock, slow clock would be 24 MHz for serialization factor 8. 192 MHz data rate is rather low, so you might also consider an implementation without DDIO registers and 192 MHz fast clock. Both should work.

Please admit that I don't have Agilex 5 support installed in my Quartus Pro tool chain (I'm on 22.4 with my present Arria 10 and Cyclone 10 GX projects), thus I can't check implementation on Agilex 5.

Actual system clock rate of your design depends on overall topology which I don't know. I expect that it's most likely higher than SERDES slow clock of 24 MHz, so you'll have an elastic buffer between SERDES and system clock domain data stream.

Regards
Frank