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sean793's avatar
sean793
Icon for New Contributor rankNew Contributor
6 months ago
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MAX10 True LVDS 1.8V Input Characteristics Before and After Configuration

I have a design in which I would like to drive LVDS clock and data from an FPGA part from another manufacturer with a specified supply voltage of 1.5V.  This LVDS signal will then be received by an A...
Configuration
Generic Io
Programmable Logic Device
  • FvM's avatar
    FvM
    6 months ago

    Hi,

    in unconfigured state, input pins are pulled towards VCCIO through weak pull-up. Current is however low and shouldn't cause problems. 

    Regards Frank

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    6 months ago

    Hi Aqid,

    thanks for correcting my previous statement. Other than most Altera FPGA, e.g. Cyclone 10 LP, MAX 10 has IO weak pull-up disabled during first configuration phase. They are turned on in second configuration phase by default, but can stay disabled with respective configuration bit option (ICB settings in programming file generation tool).

    Regards
    Frank