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sean793's avatar
sean793
Icon for New Contributor rankNew Contributor
1 month ago
Solved

MAX10 True LVDS 1.8V Input Characteristics Before and After Configuration

I have a design in which I would like to drive LVDS clock and data from an FPGA part from another manufacturer with a specified supply voltage of 1.5V.  This LVDS signal will then be received by an A...
Configuration
Generic Io
Programmable Logic Device
  • FvM's avatar
    FvM
    1 month ago

    Hi,

    in unconfigured state, input pins are pulled towards VCCIO through weak pull-up. Current is however low and shouldn't cause problems. 

    Regards Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 month ago

Hi,

in unconfigured state, input pins are pulled towards VCCIO through weak pull-up. Current is however low and shouldn't cause problems. 

Regards Frank