MAX10 pin too close to PLL clock

Question

Hi all,

I install a new Quartus 16.0 and faced with the problem that the project compilation with error message.

Error (18496): The Output CH4_TXCO in pin location 29 (pad_9870) is too close to PLL clock input pin (CLK_48MHz) in pin location 28 (pad_2)

The project uses family "MAX 10", device 10M08SAE144C8GES.

The Quartus 15 .1 project compiles fully, without errors.

How to solve a problem ? Use only Quartus 15.1 ?

Thanks.

http://www.alteraforum.com/forum/attachment.php?attachmentid=12213&stc=1

altera_forum · Answer

I have the same problem. Is there any solution?

altera_forum · Answer

You need to change CH4_TXCO pin location away from PLL clock input. SI affects to this pin because of close location to PLL clk input. So Fitter occurs error.

altera_forum · Answer

This error not occurs in Quartus 15.0 SW. So it have to have another solution.

altera_forum · Answer

Maybe device characterization seems be changed, adding restrictions. I don't know the reason.

altera_forum · Answer

I have the same question, is there any other way to solve it?

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MAX10 pin too close to PLL clock

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