Forum Discussion

Honored Contributor

9 years ago

MAX10 pin too close to PLL clock

Hi all, I install a new Quartus 16.0 and faced with the problem that the project compilation with error message. Error (18496): The Output CH4_TXCO in pin location 29 (pad_9870) is too close to ...

Altera_Forum

Honored Contributor

9 years ago

Hi,

the is case is actually documented in the MAX 10 FPGA Signal Integrity Design Guidelines (https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_sidg.pdf#page=7). The only way I can think of to get a solution for this issue in 16.0 is to file a service request.

Cheers,

fade

Forum Discussion

MAX10 pin too close to PLL clock

Recent Discussions

Agilex5 A5EB013BB23BE4S BSDL

MAX 10 FPGA Programming Failure via JTAG – nSTATUS & CONFIG_DONE as No Connect

ASx4 Interface debug in MSEL=111 (JTAG mode)

Avalon-ST configuration with Agilex 3 fails

B32A (1591) Package Mechanical Drawing