Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMAX10 pin too close to PLL clock
Hi all, I install a new Quartus 16.0 and faced with the problem that the project compilation with error message. Error (18496): The Output CH4_TXCO in pin location 29 (pad_9870) is too close to ...
Altera_ForumHonored Contributor
Honored ContributorHi,
the is case is actually documented in the MAX 10 FPGA Signal Integrity Design Guidelines (https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_sidg.pdf#page=7). The only way I can think of to get a solution for this issue in 16.0 is to file a service request. Cheers, fade
